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(January 29, 2007) RICHARDSON, Texas — ASSET InterTech, Inc., opened its first design-for-test (DFT) laboratory in Silicon Valley to validate the JTAG infrastructure on chip and PCB designs.
The lab will offer analysis of pre-prototype designs. Technicians will advise customers on effective deployment of the JTAG infrastructure in structural test applications and advanced applications such as testing high-speed AC-coupled serial buses, Intel's internal built-in self test (IBIST), system-level remote JTAG testing, concurrent programming based on the IEEE 1532 standard, and others.
With board designs becoming denser and chip geometries shrinking, applications for JTAG boundary scan will increase, said Arden Bjerkeli, director of support at ASSET, who noted that design or verification engineers are not always familiar with all points of JTAG DFT. ASSET's DFT Lab reportedly can strengthen the JTAG infrastructure in chip and circuit board designs before samples or prototypes are produced, maintaining development and production schedules and preventing redesign post-prototype.
The initial DFT Lab is located in San Jose, Calif., with Scott Creekpaum as manager. Analysis and design recommendations will be performed with ASSET's DFT Analyzer, a tool that verifies the JTAG testability of board designs automatically. BSDL Validation Service — a collaborative effort of ASSET and Agilent Technologies, Inc. (Santa Clara, Calif.) — and other tools also will be used. The lab's reports offer more than simple test coverage, explained Creekpaum. The reviews offer design recommendations that engineers can implement to improve test coverage or ensure that the JTAG infrastructure has been implemented effectively, so that other methodologies can operate concurrently.
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