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ORLANDO, Fla. — SMT Magazine will host a panel on 3D stacked packages, August 20, 2008, during SMTA International (SMTAI) in Orlando. The panel, "3D Stacked Packages: Which Way to Go?" will debate the drivers pushing innovative, small, cost-effective 3D IC concepts with through-silicon via (TSV) interconnects. Panelists from the industry, academia, and analyst firms will present and field questions on the topic.
Consumer markets are demanding smaller, lighter electronic devices with higher performance and more features. The variety of technologies and process flows surrounding miniaturization and the need to cram more functionality into smaller devices has created a dilemma among packaging experts. Everyone wants to integrate an ever-increasing number of discrete products and functions — memory, CPU, analog, RF, sensor, power — into one device. However, what format works best for each device? IC integration to SoC, 3D stacked die in chipscale packages or SiP, PoP or PiP with integrated logic and high-performance memory devices, etc. What process flow fits best for each device? Via first; before CMOS or after CMOS (and before BEOL), or via last; after BEOL (and before bonding), or after bonding.
The continuous pressure to reduce size, weight, power consumption, and cost — while increasing the functionality of portable products or advanced ICs — has driven innovative, small, cost-effective 3D IC concepts with TSVs. Accordingly, there are different motivations for the development of 3D-IC solutions: form factor to increase density, overcoming space limitations of PoP and SiP packages; shortened interconnect length to increase electrical performance and reduce power consumption; heterogeneous integration to integrate different functional layers (RF, memory, logic, MEMS, imagers, exotic substrate material, etc.) based on different optimized process nodes; and costs lower than further shrinking 2D designs.
Key technologies enabling 3D ICs with TSVs include via-formation by dry etch or laser drill; via filling; copper, tungsten, polysilicon, or conductive polymer with various process technologies; wafer thinning by grinding or etching; wafer/chip alignment and bonding; dicing by saw or laser for via-first or via-last approaches.
Panelists for "3D Stacked Packages: Which Way to Go?" include Rozalia Beica of SEMITOOL, Jan Vardaman of Techsearch Intl., Lee Smith of Amkor, and Ritwik Chatterjee of Georgia Tech PRC.
The panel will take place August 20 from 10 to 11:30 am, Cancun Room. For more information on SMTAI, visit www.smta.org.
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